In order to obtain a stable normal operation in a circuit including LSI (Large Scale Integration) and the like, it is important to have a power integrity measure in a general electronic circuit. For example, the following measure is considered. That is, to have a voltage not to fluctuate above a certain level between a supply terminal of LSI or of a semiconductor chip and an earth terminal, the impedance between the supply terminal of LSI or of the semiconductor chip and the earth terminal is kept below a certain value. This certain value (the upper limit) is called the target impedance.
In a design using a power integrity analysis system, the target impedance is specified first. Then, in a design of a printed-wiring board or an IC (Integrated Circuit) package, the impedance of these design objects is considered not to exceed the above-mentioned target impedance.
An example of a method to obtain the above-mentioned target impedance is disclosed in the following document 1.    Document 1: Smith, Larry D. et al. (August 1999) Power Distribution System Design Methodology and Capacitor Selection for Modern CMOS Technology. IEEE Transactions On Advanced Packaging 22 (3): 284-291.
The method disclosed in document 1 is a method for calculating target impedance based on the following formula.target impedance=(power-supply voltage value)×(fluctuating allowable value)/amount of LSI consumption current
In addition, there is a necessity for the target impedance to be expressed in a frequency spectrum and the amount of LSI consumption current will be expressed in frequency spectrum. That is, when in practical use, the above-mentioned formula is transformed into a Figure corresponding to the frequency spectrum. Further, the amount of LSI consumption current is represented by an instantaneous maximal current or an average amount of consumption current or the like. Furthermore, the target impedance to be evaluated will be changed whether to use the maximal current or the average current.
With the points hereof in consideration, a design method of a semiconductor device which realizes power integrity based on a calculation method of the target impedance disclosed in the document 1, is disclosed in Japanese Patent Laid-Open No. 2007-065767 (document 2).
Document 2 teaches the art of obtaining target impedance by converting known semiconductor chip characteristics or IC package characteristics and printed-wiring board characteristics to a frequency spectrum by analyzing on the time axis. Further, the design method in document 2 has a step to select one voltage fluctuation spectrum from a plurality of types of voltage fluctuation spectrum as a providing means of target impedance.
Moreover, document 2 discloses a design support system to support a design according to the above-mentioned design method. The design support system includes an adjustment target system information input unit, an adjustment target value calculation processing unit, a constraint value providing unit, a design support information determination unit, and a display unit. The adjustment target system information input unit inputs adjustment target system information of the adjustment target system which includes electrical paths in semiconductor package whereas not including semiconductor chip. The adjustment target value calculation processing unit calculates an adjustment target value of the adjustment target system being represented in a frequency domain based on the adjustment target system information. The constraint value providing unit provides a constraint value which is predetermined within the frequency domain. The design support information determination unit compares the constraint value and the adjustment target value, and determines design support information when having a section of the adjustment target value corresponding to the frequency region at which the adjustment target system exceeds the constraint value as an adjustment target section. The display unit displays the design system information.
Japanese Patent Laid-Open No. 2005-221487 (document 3) discloses a device for measuring internal impedance of a secondary battery. The device for measuring internal impedance disclosed in document 3 first obtains a number of measurement values on a time axis by having an actual measurement of input current and responsive voltage of the secondary battery, then have Fourier transformation applied to the input current and to the responsive voltage. Further, the device for measuring internal impedance evaluates each frequency component of the input current and the responsive voltage in a determined frequency, and calculates the internal impedance of the secondary battery in the determined frequency by measuring the ratio thereof.
An evaluation device for an integrated circuit device is disclosed in WO2006/109750 (document 4). The evaluation device disclosed in document 4 has an equivalent circuit creation unit, an analysis unit, and a frequency-axis/time-axis conversion unit. The evaluation device operates as follows. First, the equivalent circuit creation unit inputs a detailed composition and characteristics information of the integrated circuit device of an evaluated target, and based on the input information, creates an equivalent circuit of the integrated circuit device. Further, the equivalent circuit creation unit inputs a power-supply behavior when switching in an active circuit element of the integrated circuit device as a form of time-axis data, and converts the above to frequency axis data. Subsequently, the analysis unit calculates a power-supply voltage of each frequency by analyzing the equivalent circuit on the frequency-axis using frequency-axis data. Then, the frequency-axis/time-axis conversion unit converts the frequency-axis data which represents the power-supply voltage of each frequency to the time-axis data.